Electronic systems such as micro-processors often use clock signals to synchronize operation of their various components. Such clock signals may be comprised of a stream of timing pules that occur at a particular rate which is known as the clock rate. In many systems, the operation of each of the components is timed from a single clock signal which may be referred to as the system clock. Some circuits have various stages, or sub-circuits, each of which is timed based upon a different clock. Such circuits may use multiple clocks that have the same rate (for example, the rate of the system clock) but with a delay between the clock signals. The different clock signals used by a circuit maybe referred to as different “clock stages” and a group of such signals may be referred to as a “multistage clock.” For example, a second clock stage may be a delayed version of a first stage, a third stage may be a delayed version of the second stage, etc. Circuits that use a multistage clock may have a clock delay circuit or block that is used to delay a received clock, such as the system clock, to provide the various clock stages.
A “domino circuit” is one example of a type of circuit that uses a multistage clock. A domino circuit may be arranged with the outputs from one stage used as inputs into the next stage and with the clock delayed for each of the individual stages in order to provide a set-up time for the stages. Examples of domino circuits are self resetting domino circuits, single ended domino circuits, cascaded domino circuits, and zipper domino circuits.
In many circuits, the differential delay between clock stages determines to a large extent the delay of the logic. For some circuits, such as a cascaded differential domino circuit, it is necessary to create clock signals that have a small difference in the relative delay between stages, which may be referred to as the differential delay. These circuits may not operate properly where there is a significant difference in the relative amount of delay in the clock signals provided to different stages of the circuit. Numerous factors may impact the differential delay for the clock signals. For example, variations in the effective channel length, threshold voltage, or width of transistors in the clock delay circuit may cause differences in the delay. Device mismatches and cross-capacitance in the clock delay circuit may cause clock skew, and the delay of particular size inverter that is to be used in the clock delay circuit may vary due to process variables. In addition, there may be variations in the delay of the logic being driven by the clock signals. These and other factors have made it difficult to design and manufacture a clock delay circuit that provides clock signals with small differences in the relative delay between stages.